The present invention relates to circuitry for improving the timestamp precision in a device utilizing IEEE 1588 precision time protocol (PTP) synchronization.
IEEE 1588 provides a standard protocol for synchronizing the clocks of multiple devices that are connected via a network, such as Ethernet. IEEE 1588 is designed to provide synchronization among networked clocks which minimizes network bandwidth overhead, processing power, and administrative overhead. IEEE 1588 provides improved device synchronization through a protocol known as the precision time protocol, or PTP. PTP technology is commonly employed in Ethernet systems, wireless network routers, fiber optic communication systems and storage applications.
In communications systems, utilizing IEEE 1588 precision time protocol (PTP), a packet-based time synchronization method is defined that provides frequency, phase and time-of-day information with sub-microsecond accuracy. PTP relies on the use of carefully timestamped packets to synchronize one or more slave clocks to a master clock. With a PTP system it is necessary to measure the latency of the link between devices on a network based upon the timestamped packets. The latency measurement is an indicator of the delay that a data packet experiences while being transmitted between the network devices. The level of precision achievable using the PTP protocol depends on the variation in latency (jitter) that exists in the underlying network topology. A desired precision exists for the system latency, however the latency experienced between transmitted data packets is not always constant. Variation in the delay of data packets transmitted through the network is commonly referred to as “jitter”. Jitter within a PTP system is undesirable and as such, it is advantageous to eliminate or minimize the unwanted jitter, thereby improving the network system's timestamp precision.
Jitter results from the uncertainty of the latency between two devices that are operably coupled to one another through a data bus. The devices may be part of a single integrated circuit (IC) or may be embodied in separate ICs. Additionally, the devices may be constructed within a single IC with other devices so that the IC provides a complete system-on-a-chip (SoC) solution. For the devices of the system to communicate with one another, it is often necessary to adjust the operating frequency and data width of the data that is transmitted between the various devices on the network to allow for communication among devices that may require different data input widths. Circuitry for adjusting the width of the data transmission is known in the art, and is commonly referred to as a “gearbox”. A gearbox functions to change the data width from the input of the gearbox to the output of the gearbox. A typical gearbox includes a plurality of registers and a plurality of multiplexers operable to output data at a different width than the received input data. A gearbox may include both a transmitter gearbox and a receiver gearbox.
In a transmitter gearbox, where a larger data width must be converted to a smaller data width, the data is typically read into the gearbox as “blocks” of data having the larger data width. After a sufficient number of blocks of data have been buffered into the registers, a first portion of the first block, with the number of bits in the portion being equal to the smaller data width, is read out from the transmitter gearbox. Next, a second portion of the first block, with the number of bits in the next portion begin equal to the smaller data width, is read out. If an inadequate number of bits remain in the first block to total the smaller data width, bits are read from a first portion of a second data block to total the smaller data width. This process continues until an integral number of blocks have been read and then the process repeats.
In a receiver gearbox, where a smaller data width must be converted to a larger data width, the data is read into the gearbox as blocks of data having the smaller data width. After a sufficient number of blocks of data have been buffered into the registers, all or a portion of each of the buffered blocks are concatenated and read out to equal the number of bits to make up the larger data width. The remaining portion of data in the last block read is then shifted through the registers and additional data is read into the gearbox registers at the smaller data width. This continues until an integral number of blocks have been read out and then the process repeats.
Utilizing a gearbox for data conversion from one data width to another data width within the network system introduces jitter into the data path because the time required to process data through the gearbox is not the same for every data packet. As such, the variation in the delay, or latency, of data packets transmitted through the gearbox causes undesirable jitter in the system. It is desirable to eliminate or minimize this variation and thereby improve the timestamp precision of the PTP system.
In light of the above, a need exists for a system and method to improve the timestamp precision in a PTP device or system. A further need exists for minimizing the jitter resulting from a gearbox employed in a PTP system.